A fiber optic communications link typically includes a transmitter to transmit and direct through a fiber optic cable light emitted from a laser diode. At the receiving end of the fiber optic cable the light is detected by a photo detector and converted into an electrical current. The current is converted to voltage by a transimpedance amplifier and then amplified by a limiting amplifier. The amplified voltage signal is applied to a clock and data recovery circuit which extracts a clock signal from the received data (i.e., a recovered clock signal) and acquires the frequency of the incoming data by comparing the frequency of the recovered clock signal to the frequency of the incoming data signal.
Frequency acquisition is performed with a frequency lock loop (FLL) circuit which typically includes a frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO) and a digital divider.
One typical implementation of the frequency detector is a rotational frequency detector (RFD). The RFD locks the frequency of the recovered clock signal (fVCO/N) to the frequency of the incoming data signal by comparing transitions of the data signal to transitions of the recovered clock signal to determine if the frequency of the recovered clock signal (fvco/N) needs to be increased or decreased. The RFD then generates the appropriate frequency up or frequency down signals (or pulses) which are applied to the charge pump. The charge pump adds or removes charge to or from the loop filter which applies an increase or decrease in the voltage to the VCO. The VCO then increases or decreases its output frequency proportional to the amount of voltage applied to it, known as the frequency step size. The time required to lock the frequency of the recovered clock to the incoming data is known as acquisition time.
Prior art RFDs produce frequency up and frequency down pulses whose width is equal to one period of the recovered clock, i.e., fVCO/N. Because the frequency of the input data signal can vary significantly in wide band applications, the value of N generated by the digital divider (e.g., between 1 and 256) also varies with the changes in frequency, e.g., at high frequencies, N is lower. The result is the pulse width of the frequency up and frequency down signals generated by prior art RFDs also varies directly with the changes in N. Therefore, at low values of N, the pulse width of the frequency up or frequency down signals produced by these prior art RFDs is very small which overworks the charge pump requiring a higher speed and more complex design of the charge pump. Moreover, the resulting narrow pulse width frequency up signals and frequency down signals applied to the charge pump result in a very small frequency step size produced by the VCO which increases acquisition time of the frequency locked loop (FLL).
Another drawback associated with prior art RFDs is that the operating range of the normalized frequency error of these RFDs is between −37% to +50%. If the frequency difference between the incoming data and the recovered clock is outside these limits, the RFD will not function correctly and will not force the frequency of the recovered clock (fVCO/N) to be equal to the frequency of the data. Although in some applications this is not a problem, as the circuit may be designed to be centered at the expected data frequency and varies little around that point, in other applications, such as wide-band applications, this is unacceptable.
Yet another drawback of conventional RFDs is that when the normalized frequency error is less than approximately −50% no output is produced which results in a condition that is indistinguishable from a true lock. This can result in a false lock condition. Also in frequency locked loops which employ RFDs, a residual frequency error exists between the recovered clock signal (fVCO/N) and the incoming data signal when the loop has settled. In frequency locked loops which employ conventional RFDs, this residual frequency error is a function only of the charge pump current and the leakage current at the loop filter node.